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-- Company: 
-- Engineer:
--
-- Create Date:   11:11:38 03/26/2010
-- Design Name:   
-- Module Name:   C:/EGR426Projects/microcontroller/cpu_test.vhd
-- Project Name:  microcontroller
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: cpu
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY cpu_test IS
END cpu_test;
 
ARCHITECTURE behavior OF cpu_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT cpu
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         Inport0 : IN  std_logic_vector(7 downto 0);
         Inport1 : IN  std_logic_vector(7 downto 0);
         Outport0 : OUT  std_logic_vector(15 downto 0);
         Outport1 : OUT  std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal Inport0 : std_logic_vector(7 downto 0) := (others => '0');
   signal Inport1 : std_logic_vector(7 downto 0) := (others => '0');

 	--Outputs
   signal Outport0 : std_logic_vector(15 downto 0);
   signal Outport1 : std_logic_vector(15 downto 0);

   -- Clock period definitions
   constant clk_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: cpu PORT MAP (
          clk => clk,
          reset => reset,
          Inport0 => Inport0,
          Inport1 => Inport1,
          Outport0 => Outport0,
          Outport1 => Outport1
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ms.
      wait for clk_period;
		reset <= '1';
      wait for clk_period;
		reset <= '0';
		wait for clk_period;
      -- insert stimulus here 

		wait for clk_period*3;
		Inport0 <= "00000001";

		wait for clk_period;
		Inport0 <= "00000011";
		
		wait for clk_period;
		Inport0 <= "00000010";
		
		wait for clk_period*2;
		Inport0 <= "00000000";
		
      wait;
   end process;

END;
